1. Technical Field
The present invention relates to integrated circuit testing, and more particularly, to scan testing of integrated circuits.
2. Description of Related Art
During design of an integrated circuit, the design (typically a software modeled design) is extensively tested for proper functioning. The testing at this stage of development is known as design verification testing. Although integrated circuit designs are thoroughly tested during the design phase, once the integrated circuits are fabricated, they must be individually tested for manufacturing defects as well as for operation and functionality.
Referring to FIG. 1, one popular method for providing individual testing is referred to as “scan testing” in which test data (e.g., input test data vector 110a; output test data vector 112a) is shifted through serially connected registers 102a (e.g., input-side registers 102a(1-3); output-side registers 102a(4-6)) on the input-side and output-side of a logic 104a under test within an integrated circuit 100. Input-side registers 102a(1-3) are connected in series to form a shift register known as a scan chain 101a, which is connected to access ports 106a(1-2) via interconnects 108a(1-4). Similarly, output-side registers 102a(4-6) form another scan chain 101b, which is connected to access ports 106a(3-4) via interconnects 108a(11-14). After input-side registers 102a(1-3) are loaded with input test data via access port 106a and interconnects 108a(1-3), the input test data is applied to logic 104a via interconnects 108a(5-7) in generating corresponding output test data, which is captured in output-side registers 102a(4-6) via interconnects 108a(8-10). This output test data (e.g., output test data vector 112a) is then serially shifted out via access port 106a4 and interconnects 108a(12-14) from output-side registers 102a(4-6) for observation.
The speed at which scan testing can be performed generally depends on how quickly input test data is applied to the logic and how quickly corresponding output test data from the logic is received for observation. For example, referring again to FIG. 1, three clock cycles are required to load the three 1-bit input-side registers 102a(1-3) with a 3-bit input test data (e.g., 1,0,1). An additional clock cycle is required for applying the input test data from input-side registers 102a(1-3) to logic 104a and for output-side registers 102a(4-6) to receive a corresponding 3-bit output test data (e.g., 0,0,1) from logic 104a. Then, three clock cycles are further required for shifting out the output test data from output-side registers 102a(4-6). That is, a total of seven clock cycles are required for applying the input test data vector to the logic and for receiving the corresponding output test data vector for observation. If the logic is to undergo further scan testing, another seven clock cycles would be needed to apply each subsequent input test data vector in series to the logic and for receiving the corresponding output test data vector for observation. As such, scan testing can be a very time consuming process, especially as the number of input-side or output-side registers of a scan chain is increased.
In a system on a chip (SOC) or system on a programmable chip (SOPC), there may be multiple blocks of logic or embedded cores that can only be accessed through scan at their input and output access ports for test purposes. For example, embedded blocks with tight timing margins may only be accessed through scan at their input and output access ports and not immediately at their internal registers. Since scan testing involves a serial operation where each test data vector is shifted in only after the previous test data vector is shifted out for observation, scan testing time is exacerbated for these types of blocks or cores.
Thus, there is a need for techniques and mechanisms that can improve the speed at which scan testing of manufactured integrated circuits can be implemented, thereby improving the scan testing time.